• The effective gate capacity reaches 19 million gates;

• With 76,000 6-input adaptive LUTs;

• With 152,000 programmable registers;

• Equipped with 616 ded memory units of 9.2Kbit (including parity bits), capable of achieving up to 5667Kbit of dual-port RAM;

• With 616 high-speed 18bit18bit multipliers;

• High-speed clock management function d on PLL clock generator;

• 6 programmable PLLs, each supporting 5 programmable outputs;

• The global clock system supports 16 main trunk clocks, with 4x4 modules able to  any 8 of them;

• Up to 278 programmable user I/Os, including 70 HD IOs and 208 HP IOs;

• Support various I/O standards: LVCMOS, SSTL protocol standards under multiple voltage standards of 3.3V/2.5V or 1.8V/1.5V;

• DDR IO provides 78 pairs of LVDS standard differential ports;

• The transmission rate of the high-speed serial interface reaches 28Gbps, supporting the following high-speed interface protocols:

• Hard-core PCIe controller and Hard-core Ethernet controller;

• Provides Native interface, supporting users to implement SATA3.0, Serial RapidIO4.0, USB3.1, JESD204C, DP1.4, QSGMII, Aurora, 25G-R/KR, and etc.;

• Supports DDR4 and MIPI-DPHY;

• Supports SBVB484, FFVB676.