• Single-core LS232, MIPS32 instruction set compatible, main frequency 300MHz;

• 16KB data cache and 16KB instruction cache;

• Program Memory NORFLASH2;

• Data Memory SDRAM3;

• FPGA logic gates: 3.5 million gates;

• Data cache space: 128MB, with EDAC;

• Program storage space: 16MB, with EDAC;

• User-programmable I/O: no less than 120;

• Temperature range: -55～+125℃;

• Total ionizing dose (TID): TID > 150 Krad(Si);

• SEL) threshold: SEL > 75MeV·cm2/mg;

• Single Event Upset (SEU) threshold: soft error probability ≤ 10-10 error/bit/day.